Formal Verification of PowerPC(TM) Arrays using Symbolic Trajectory Evaluation
نویسندگان
چکیده
assertions IMPLEMENTATION
منابع مشابه
Automatic Generation of Assertions for Formal Veri cation of PowerPC Microprocessor Arrays Using Symbolic Trajectory Evaluation
For verifying complex sequential blocks such as microprocessor embedded arrays, the formal method of symbolic trajectory evaluation (STE) has achieved great success in the past [[3], [5], [6]]. Past STE methodology for arrays requires manual creation of \assertions" to which both the RTL view and the actual design should be equivalent. In this paper, we describe a novel method to automate the a...
متن کاملFormal Verification of a Superscalar Execution Unit 1
Abstract. Many modern systems are designed as a set of interconnected reactive subsystems. The subsystem verification task is to verify an implementation of the subsystem against the simple deterministic high-level specification of the entire system. Our verification methodology, based on Symbolic Trajectory Evaluation, is able to bridge the wide gap between the abstract specification and the i...
متن کاملVerifying Nondeterministic Implementations of Deterministic Systems1
Abstract. Some modern systems with a simple deterministic high-level specification have implementations that exhibit highly nondeterministic behavior. Such systems maintain a simple operation semantics at the high-level. However their underlying implementations exploit parallelism to enhance performance leading to interaction among operations and contention for resources. The deviation from the...
متن کاملVerifying Safety Properties of a Powerpc Tm ? Microprocessor Using Symbolic Model Checking without Bdds ??
In 1] Bounded Model Checking with the aid of satissability solving (SAT) was introduced as an alternative to symbolic model checking with BDDs. In this paper we show how bounded model checking can take advantage of specialized optimizations. We present a bounded version of the cone of innuence reduction. We have successfully applied this idea in checking safety properties of a PowerPC microproc...
متن کاملFormal Veri cation of Memory Arrays
Veri cation of memory arrays is an important part of processor veri cation. Memory arrays include circuits such as on-chip caches, cache tags, register les, and branch prediction bu ers having memory cores embedded within complex logic. Such arrays cover large areas of the chip and are critical to the functionality and performance of the system. Hence, these circuits are custom designed at the ...
متن کامل